1. Field of the Invention
This invention relates in general to digital timing circuits, and more particularly to a digital phase locked loop capable of recovering a clock signal from a choice of inputs signals subject to jitter.
2. Description of Related Art
In digital networking applications, there is a requirement to provide timing reference for the SONET (synchronous optical network) OC-N and STS-N interface circuits, and TI or El primary rate digital transmission links. These timing signals must meet relevant standards such as BELLCORE GR-1244-CORE and GR-253-CORE recommendations for STRATUM 3E, 3 and 4E clocks and SONET Minimum Clock (SMC). These specifications impose stringent requirements on the transfer characteristics between the input references and the generated output clocks, and in particular they specify limitations on phase perturbations that may be generated on output clocks as a result of switching between input references.
The method of providing such timing signals is to use a phase locked loop. Typically, this consists of a phase detector comparing the input reference signal with the output of the loop divided by a suitable factor, a loop filter to eliminate high frequency fluctuations, and a controlled oscillator whose frequency is controlled in such a way as to eliminate the phase difference detected by the phase detector.
U.S. Pat. No. 5,602,884 discloses a phased locked loop using a combination of a DCO clocked by a 20 MHz clock and a tapped delay line. Since the DCO directly controls the tapped delay line, jitter free precision can be maintained to a fraction of a clock cycle. The fraction is limited by the delay time of each tap of the tapped delay line.
The conventional approach to minimizing phase perturbations on the output clocks as described in this patent is as follows: Rather than connecting the phase comparator directly to the active input reference a intermediate circuit is connected between the input reference and the phase comparator. This intermediate circuit contains an up/down counter clocked by a relatively high speed clock synchronous with the generated output clocks. The output of this counter produces a virtual reference which subsequently goes to the phase comparator. Upon activation of a reference rearrangement the following sequence of events occurs. The PLL is placed in holdover mode. The phase difference between the output clock and the assigned reference clock is calibrated by counting high speed clock cycles. This value is subsequently subtracted from the counter in producing the virtual output reference clock. The PLL is subsequently taken out of holdover and aligns to the newly conditioned virtual reference. In this manner phase offsets between the reference clocks can be built out.
The fundamental disadvantage of this approach is that the resolution of the phase build out is proportional to the frequency applied to the counter. The circuit may still generate a phase excursion on the output clocks up to a size equal to the period of the high speed clock. The maximum size of the phase excursion can only be reduced by increasing the speed of the high speed clock, the size of the phase build out counter and therefore the number of gates required and power consumption of the circuit.
An object of the invention is to provide a phase locked loop with a reference switching mechanism that alleviates the aforementioned problems with prior art.
Accordingly the present invention provides a clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, comprising an acquisition phase locked loop (PLL) for each input, each said acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from said phase comparator, said first DCO of said acquisition PLL being in a feedback loop to supply an input to said phase comparator and said second DCO of said acquisition PLL having a control input to introduce a phase offset therein relative to said first DCO of said acquisition PLL and providing an output for said acquisition PLL; an output PLL having a phase comparator selectively connectable to the output of each of said acquisition PLLs, said output PLL having a first DCO providing an output for said circuit and a second DCO in a feedback loop providing a feedback signal to said phase comparator of said output PLL, said second DCO of said output PLL having a control input to introduce a phase offset therein relative to said first DCO of said output PLL; and a control unit for setting the phase of the second DCO of said acquisition circuit and the second DCO of said output PLL to a common value during changeover from one input to another to avoid an instantaneous phase error upon switching reference signals.
The DCOs are preferably adding rate multipliers, one of which generates an output signal upon attainment of an overflow condition and a remainder generating a time error signal, and the other of which has a settable phase.
The feedback loop preferably includes a tapped delay line to reduce jitter.
Since each PLL has two DCOs, only one of which is in the feedback loop, during changeover of input signals it is possible to eliminate the phase error between the settable DCOs and thus prevent phase jumps occurring upon change of input.
The invention also provides a method of recovering a clock signal from one of a plurality of input reference signals comprising the steps of providing an acquisition phase locked loop (PLL) for each input, each said acquisition PLL including first and second digital controlled oscillators (DCOs); tracking a reference input signal with said first and second DCOs, said first DCO being in a feedback loop of said acquisition PLL and said second DCO providing an output of said acquisition phase locked loop; providing an output PLL selectively connectable to said acquisition PLLs, said output PLL including first and second DCOs; tracking said output of said acquisition PLLs with said first and second DCOs of said output PLL, said first DCO of said output PLL providing a recovered clock signal and said second DCO of said output PLL being in a feedback loop of said output PLL; and setting the phase of said second DCO of said acquisition PLL and said output PLL to a common value during changeover to another reference input.